Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Hierarchical test is a methodology that lets you perform most of the DFT work at the block level instead of at the flattened top level of the design. It is not a new approach. In fact, I’ve seen ...

Watch the video below, where Lee Harrison – Director of Automotive IC Solutions at Siemens EDA – explains the technology behind full In-System ATPG testing for advanced semiconductors Continuous ...

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...

The infrastructure around semiconductor testing is changing as companies build systems capable of managing big data, utilizing real-time data streams and analysis to reduce escape rates on complex IC ...

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and ...