Design-Reuse

DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology

HiDFT-Scan Analyzes, Implements Scan Test Structures in Register-Transfer Level Designs; Closes Historical Gap between RTL and DFT PALO ALTO, Calif.--October 22, 2007--DeFacTo Technologies today ...
Semiconductor Engineering

No-Compromise Packetized Test Improves DFT Efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
Semiconductor Engineering

Optimizing Scan Test For Complex ICs

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...