Chip designs today have more functionality, more black-boxed intellectual property (IP) and shorter tape-out schedules. However, they require even more design verification than in the past, which ...

This paper describes the process and tools used in the verification of a family of Secure Digital (SD) IP cores. The verification process described included SystemC verification, RTL simulation and ...

Two trends are conspiring to make complex modern chip development more and more difficult: the increasing amount of software content required for what are essentially monolithic embedded systems, and ...