Macraigor Systems LLC's usb2Demon and usb2Sprite, two new USB 2.0 JTAG debug interface devices are identical in functionality but differ in speed to provide embedded developers with flexibility in ...

J-LINK REDUCES JTAG DEBUG PINCOUNT FROM 5 to 1! Pittsford, New York—Traditional JTAG boundary-scan testing normally takes up 5 valuable pins on an i.c., requires 5 resistors, and increases chip power.

Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count ...

Design tool firm Altium’s latest JTAG interface is intended to allow system developers to use the firm’s Nexar test tool with their existing FPGA development boards to interactively design and debug ...

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...

Over the last year or so we’ve noticed a definite uptick in the number of folks using OpenOCD on the Raspberry Pi. It’s a cheap and convenient solution for poking around with various microcontrollers ...

The PowerPC started out as a RISC challenger to the PC's XC86, developed by Apple, IBM, and Motorola. It lost that race, but it has become a major RISC for ICs, ASSPs, and cores. PowerPCs have a large ...

Intel(R) System Studio Developer Story : With XDB and MinnowBoard MAX , how to debug exception errors in the Android-Linux-Kernel. In this article, we can see how to ...

New capabilities for improving embedded control and visibility for chip level analysis and design for debug logic and interfaces to an IC are needed to enable real time functional control, test, and ...