Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

In the previous blog (Synchronization techniques for multi-clock domain SoCs& FPGAs), we studied different types of synchronization techniques to synchronize signals from one clock domain to another.

Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies. Many modern ...

The IEEE 1588 Precision Time Protocol enables precise time synchronization over the packet-based Ethernet network so that the time on a slave clock at one end of the network agrees with a master clock ...

Many of today's system-on-chip (SoC) designs cause significant problems and delays as they go through the physical design process. Yes, physical design is harder than ever. But part of the problem is ...