GitHub

This project implements a 4-bit Unsigned Parallel Multiplier in Verilog

📌 Overview Unlike a serial multiplier, a parallel multiplier generates all partial products simultaneously and adds them using combinational adders to produce the final result in a single clock cycle ...
IEEE

Bit-Width Agnostic Parallel In-Memory Adder with O(1) Latency Using STT-MRAM

Abstract: This paper introduces a novel in-memory adder architecture based on Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) to perform high-speed parallel addition with ...
GitHub

Monster Adders: High-Frequency 2048-bit Adders on Intel Agilex 5 FPGAs

A high-performance FPGA implementation of 2048-bit binary adders optimized for maximum clock frequency on Intel Agilex 5 devices. This project explores and compares two distinct architectural ...