GitHub

nandyala-ananya/4bit-synchronous-updowncounter-with-7-segment-display

This project implements a 4-bit synchronous up/down counter designed and simulated using NI Multisim. The counter counts either up or down based on a control input and displays the current count on a ...
EDN

4-bit Counter

Designed a 4-bit counter using a J-K flip-flop that has a clocked input with reset. Performed simulations of various output parameters like rise time and fall time. The design is done using cadence ...
IEEE

Synchronous Up/Down Counter Using Clocked CMOS Toggle Flip-Flop With 3T-SAPON Technique For Low Power Consumption

Abstract: In this paper, 16 bit counter that operates with low power consumption in a synchronous manner is designed. Counter is designed with different segments namely local clock generator(LCS), ...
IEEE

Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part I

Abstract: This paper is Part I of a two-part study of systematic procedures for realizing synchronous sequential machines using flip-flop memory. In this study the methods of Dolotta and McCluskey, ...