Business Wire

Keysight’s New Parallel Parametric Test System Delivers High Throughput and Cost-Effective Wafer Test

SANTA ROSA, Calif.--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to ...
Business Wire

Keysight Introduces Massively Parallel Board Test System to Enable Higher Throughput in a Smaller Footprint

SANTA ROSA, Calif.--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that helps enterprises, service providers and governments accelerate innovation to connect ...
EDN

Parallel parametric test goes asynchronous

Parallel test is a surefire method for speeding up production, and asynchronous parallel test has long been known as an effective way of significantly improving through-put while making the most of ...
Semiconductor Engineering

Site-To-Site Variation In Parallel Test

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An ...
Semiconductor Engineering

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...