EDN

SystemC standards group releases transaction-level modeling standard

SystemC standards group Open SystemC Initiative (OSCI) has released the SystemC TLM (transaction-level modeling) standard version 1.0. The TLM standard kit, which can be downloaded under an open ...
Design-Reuse

Modelling OCP Interfaces in SystemC: Standards built on top of OSCI's TLM-2

OSCI has recently published their TLM-2.0 technology which provides for interoperability between SystemC models of electronic components whose primary interfaces are memorymapped busses. This is a ...
Design-Reuse

Open SystemC Initiative Announces Completion of New Standard Enabling the Real-World Interoperability of Transaction-Level Models

Much anticipated TLM-2.0 provides essential framework for standards-based ESL design ANAHEIM, Calif.-- June 09, 2008-- The Open SystemC Initiative (OSCI), an independent non-profit organization ...
EDN

Fit the hardware to the algorithm with SystemC models

System-on-chip (SoC) designs commonly consist of one or multiple processors (e.g. DSP or reduced instruction set computing (RISC) processors), interconnects, memory sub-systems, DSP hardware ...
Electronic Design

SystemC Model Library Makes TLM Reuse Easier

Would-be users of transaction-level models (TLMs) and electronic system-level (ESL) design approaches in general face a major hurdle. Traditionally, it has been difficult to construct TLMs that serve ...
Semiconductor Engineering

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, ...
Business Wire

Reference Virtual Platform of ARM Model Running Linux Under SystemC/TLM-2.0 Released by Open Virtual Platforms (OVP)

THAME, England--(BUSINESS WIRE)--The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of a reference virtual platform of the ARM Integrator development board using ...
Semiconductor Engineering

TLM 2.0: Necessary for Co-Simulation

Transaction-level modeling – an abstracted representation of design IP above the RT level — continues to grow in importance for architectural exploration, performance analysis, building virtual ...
uni

SystemC to Timed Automata Transformation Engine (STATE)

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...
Electronics Weekly

ARM supports SystemC with co-verification model library

ARM has once again put its weight behind SystemC as the much-needed industry standard design and verification language to support designers of multi-sourced IP, announcing the RealView model library.