EDN

ARM adds VLSI test at Indian design center

BENGALURU, India — ARM has set up a VLSI test lab at its design center here to analyze intellectual-property libraries and ARM physical IP, so as to correlate design to silicon behavior. Such activity ...
CIOL

ARM Bangalore center gets VLSI test lab

BANGALORE, INDIA: ARM Holdings, the world's leading semiconductor intellectual property (IP) supplier has announced launch of its Very-large-scale integration (VLSI) test lab set up at a cost of $1 ...
EDN

Call for Papers: VLSI Test Symposium

The IEEE's Test Technology Technical Council (TTTC) has extended the deadline for paper submissions for the 2003 IEEE VLSI Test Symposium, slated for April 27 to May 1 in Napa Valley, CA. Paper ...
Design-Reuse

SoC Test and Verification -> ATE struggles to keep pace with VLSI

The cost of testing complex system-on-chip designs will soon surpass the cost of manufacturing them. Clearly this is an unstable situation. It is simply too hard to keep up with Moore's Law. While the ...
TechRepublic

Reordering Algorithm for Minimizing Test Power in VLSI Circuits

Power consumption has become a crucial concern in Built-In Self-Test (BIST) due to the switching activity in the Circuit Under-Test (CUT). In this paper, the authors present a novel method which aims ...
IPWatchdog

VLSI Scores Reversal of Noninfringement Rulings Against Intel at CAFC

The U.S. Court of Appeals for the Federal Circuit (CAFC) today issued a precedential decision authored by Chief Judge Moore ...