Design-Reuse

Synopsys' coreAssembler Tool Decreases Design Time for Leading Semiconductor Companies by up to 67 Percent and Significantly Reduces SoC Cost

Tool Enables Designers to Rapidly Configure and Assemble SoCs from Pre-Designed and Packaged IP Blocks DESIGN AUTOMATION CONFERENCE, San Diego, Calif., June 7, 2004-- Synopsys, Inc. (Nasdaq:SNPS), the ...
Design-Reuse

Synopsys' coreAssembler Reduces Time and IP Integration Risk for Spirit-Compliant IP

MOUNTAIN VIEW, Calif. - March 8, 2005- Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that Synopsys' coreAssembler intellectual property (IP) ...
Electronic Design

Get In The Spirit Of IP Reuse

Anyone embarking on an SoC design knows that the job involves stitching together relatively large blocks of IP. That may sound like a relatively easy task, but anyone in-the-know will tell you it's ...
New Electronics

Building an IP-XACT design and verification environment with DesignWare IP

With more IP components and growing time to market pressures, designers are looking for a way to build and update SoC designs easily. IEEE1685 (IP-XACT) was designed to fit this requirement and ...