The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

There are many ways to categorize engineers—to “slice and dice” them, if you will. I’m speaking figuratively, of course (we don’t want anyone to get any unfortunate ideas…especially since… the ...

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Axiomise, the leading provider of cutting-edge formal verification consulting, training, services, and IP, today unveiled a comprehensive introductory certification-based formal verification training ...

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...

The urgency for change: Are traditional DRC debug flows enough? Physical verification engineers know all too well the reality of debugging massive integrated circuit (IC) designs. For years, the ...

Michael Engle is Cofounder at 1Kosmos and was previously head of InfoSec at Lehman Brothers and Cofounder of Bastille Networks. In November 2023, CISA issued a critical security advisory revealing how ...