Design-Reuse

Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often

Because today’s System-On-Chip (SOC) designs contain millions of transistors, design engineers must treat power dissipation as an important design goal for IP blocks and not as just a data-sheet ...
Design-Reuse

Accurate System Level Power Estimation through Fast Gate-Level Power Characterization

Low power consumption is becoming a critical factor for System-on-a-Chip (SoC) designs. System level power estimation for SoCs has gained importance with the increase of SoC design complexity. This ...
EDN

Estimating Power Dissipation in CMOS Devices

This application note describes ways to estimate power dissipation of individual CMOS logic devices in a system. It will help users determine if their designs raise any power dissipation concerns. Due ...
Semiconductor Engineering

Design Considerations For Ultra-High Current Power Delivery Networks

This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power ...