EDN

SPICE-based stochastic design of SRAM Array considering PVT variations

Seeking an internship position during the summer of 2011 in the area of Digital ASIC Design with focus on Front-end design, Verification or Layout. Obtained Bachelor’s degree in Electronics ...
Design-Reuse

sureCore Delivers Customised Low Power SRAM for Data Intensive Designs

SHEFFIELD, England, Mar. 21, 2019 – sureCore Limited's new SureFit SRAM customization service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...
Design-Reuse

A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design

In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of ...
Semiconductor Engineering

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled “Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution”, from researchers at Univ.
Electronic Design

10T SRAM Circuitry Clocks at 3.1 GHz

This file type includes high resolution graphics and schematics when applicable. Memory plays a continually more important role in digital and mixed-signal circuits, but a key for future designs is ...
Semiconductor Engineering

Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments

On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is ...