Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more ...
EDN

‘Wrap’ your cores to enable SoC test

Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies ...
EDN

Design holds the key to cost-effective SOC testing

As device complexity grows and fabrication costs continue to fall, test is emerging as the largest expense in complex SOC (system-on-chip) IC manufacturing. At the same time, ICs continue to ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
Semiconductor Engineering

Supporting Multiple Time Domains In SoC Production Test

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for ...
SDxCentral

QuSecure Achieves SOC 1 and SOC 2 Type 2 Compliance Validating Security Controls and Practices of its Leading Post-Quantum Cryptography Solution

Independent, Third-Party Auditors Validate QuProtect’s Operation Aligning Securely and Consistently with Common Security Policies and Requirements SAN MATEO, Calif.--(BUSINESS WIRE)--#PQC--QuSecure™, ...