SAN MATEO, Calif. — Sequence Design Inc. has introduced a static timing analysis tool that accounts for inductance delay and IR drop in ASICs and system-on-chip designs. In addition, the company has ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...

In the move to ultradeep-submicron processes-at 0.25- micron design rules or below-system-on-chip designers are finding new challenges in achieving timing closure. Chief among these are timing ...

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...